Synchronization signal processor

ABSTRACT

A video data stream containing picture video and a vertical synchronization signal is processed in a microprocess that performs statistical evaluation of the frequency of the vertical synchronization signal of the video data stream. The statistical evaluation includes producing the statistical mean value and variance of the frequency of the vertical synchronization signal.

This application claims the benefit of the priority date of U.S.Provisional patent application Ser. No. 60/375,504, filed Apr. 25, 2002.

FIELD OF THE INVENTION

This invention relates to a synchronization signal processingarrangement in a video display apparatus.

BACKGROUND OF THE INVENTION

A typical television receiver includes a detector for producing from aninput signal an analog, base-band television signal in accordance withthe standard used. The analog, base-band television signal includes ahorizontal synchronization signal, a vertical synchronization signal anda video portion signal. In a digital television receiver, the base-bandtelevision signal is applied to a digital signal processor for producinga video data stream in accordance with, for example, the BT 656standard. The video data stream includes a corresponding verticalsynchronization signal.

When the input signal is absent or too weak, the video data stream willcontain invalid data. It may be desirable to detect whether the inputsignal is absent or too weak. For example, when the input signal isabsent or too weak, the detection can be used for blanking the displayscreen and displaying a banner for the user that indicates absent or tooweak input signal.

In carrying out an inventive feature, the video data stream is processedin a microprocessor that performs statistical evaluation of thefrequency of the vertical synchronization signal of the video datastream. The statistical evaluation includes computing the statisticalmean value and variance of the frequency of the vertical synchronizationsignal.

SUMMARY OF THE INVENTION

A video display apparatus, embodying an inventive feature, includes asource of a periodic synchronization signal for synchronizing anoperation of a display device responsive to an accompanying video signalthat provides picture information. A utilization circuit operates in anormal operation mode, when the synchronization signal is valid, and ina second operation mode, when the synchronization signal is invalid. Aprocessor is responsive to the synchronization signal and coupled to theutilization circuit for producing a value indicative of a statisticalvariance of a frequency of the synchronization signal to change the modeof operation of the utilization circuit from the normal operation modeto the second operation mode, when the statistical variance exceeds afirst threshold value.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 illustrates a block diagram of a digital television receiver,embodying an inventive feature;

FIG. 2 illustrates a flow chart of a first portion of a routineperformed in the arrangement of FIG. 1; and

FIG. 3 illustrates a flow chart of a second portion of the routineperformed in the arrangement of FIG. 1.

DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a block diagram of a digital television receiver,embodying an inventive feature. A conventional Tuner/IF stage 66includes a detector, not shown, for producing from a radio frequency(RF) input signal 65 that is coupled via an antenna, not shown, ananalog, base-band video signal 67 in accordance with the standard used,for example, the standard in the United States known as NTSC. Base-bandvideo signal 67 is applied to a video decoder 68 for producing, in aconventional manner, a video data stream CCIR 656. Video data streamCCIR 656 is produced, in accordance with, for example, the BT 656standard, in a conventional manner. Video decoder 68 may include anintegrated circuit (IC), for example, ADV7185 or BT819. Video datastream CCIR 656 is coupled to a video processor 69 that may include anIC TL851 for generating, for example, a Red, Green and Blue (R, G, B)video signal RGB that is coupled to a display 64 having a displayscreen, not shown.

Video data stream CCIR 656 includes a horizontal synchronization signal,a vertical synchronization signal VSYNC, shown schematically in FIG. 1,and a video portion signal, not shown. Video processor 69 alsogenerates, in a conventional manner, a program interrupt signal, notshown, that is coupled to a microprocessor unit 73 via an internal bus70 and a bus master 72 operating as a bus bridge, each time verticalsynchronization signal VSYNC occurs. A memory 71 is shared bymicroprocessor unit 73 and video processor 69.

FIG. 2 illustrates a flow chart of a first portion of a routineperformed in each time vertical synchronization signal VSYNC occurs invideo stream CCIR 656 of FIG. 1. Similar symbols and numerals in FIGS. 1and 2 indicate similar items or functions. The routine of FIG. 1 isinitiated in microprocessor unit 73 via, for example, the aforementionedprogram interrupt signal.

In the first portion of the routine of FIG. 2 performed inmicroprocessor unit 73 of FIG. 1, a word SyncCounter of FIG. 2 forcounting the occurrences of vertical synchronization signal VSYNC in apredetermined interval such as, for example, a 1-second interval isincremented each time vertical synchronization signal VSYNC occurs, asshown in a step 201. Additionally, the length of an interval INTERVALthat has elapsed from the immediately preceding occurrence of verticalsynchronization signal VSYNC, as shown in a step 202, is measured andstored in a corresponding word SaveInterval [Index] and an index wordIndex is incremented, as shown in a step 203. The lengths of, forexample, only the last 10 timing intervals INTERVAL contained in words,SaveInterval [1]-SaveInterval [10], are available for further processingby microprocessor unit 73 of FIG. 1. This is implemented by performingthe operation, Index=mod (Index, 10), as shown in a step 203 of FIG. 2,where the term mod(Index, 10) refers to 10 modular operation.

FIG. 3 illustrates a flow chart of a second portion of the routineperformed in microprocessor unit 73 of FIG. 1, at the end of theaforementioned 1-second interval. Similar symbols and numerals in FIGS.1, 2 and 3 indicate similar items or functions. As a result of theoperations performed in the routine of FIG. 2, word SyncCounter of FIG.2 contains the number of occurrences of vertical synchronization signalVSYNC, during the immediately preceding 1-second interval. Thus, wordSyncCounter is indicative of the frequency of vertical synchronizationsignal VSYNC.

Word SyncCounter of FIG. 3 is compared to a value equal to one quarterof a value N or N/4, where “N” is the expected value of word SyncCounterwhen the frequency of vertical synchronization signal VSYNC is equal tothe expected frequency, as shown in a step 301. Value N that isdetermined by the expected frequency of the input signal may bedifferent for different modes of operation. For example, when theexpected frequency of vertical synchronization signal VSYNC is 30 Hz,the value of N for the aforementioned 1-second interval is equal to, forexample, 30.

Similarly, word SyncCounter is also compared to a value equal to 3 timesN or 3N, as shown in a step 302. If the value of word SyncCounter isoutside the range, (N/4<word SyncCounter<3N), the frequency of verticalsynchronization signal VSYNC is considered to be outside an acceptablerange and the input signal is deemed to be absent or too weak, as shownin a state 307 via a path 301 a and via a path 302 a. If the value ofword SyncCounter is within the range, (N/4<word SyncCounter<3N),microprocessor unit 73 performs statistical evaluation of the frequencyof vertical synchronization signal VSYNC, as follows.

For saving computing power and time, only, for example, the last 10timing intervals contained in words, SaveInterval [1]-SaveInterval [10],are used for computing a mean value MEAN and a variance value VARIANCEof the period of vertical synchronization signal VSYNC, as shown in astep 303.

In carrying out an inventive feature, value VARIANCE is indicative ofthe extent of fluctuation of the frequency of sync signal VSYNC from theaverage frequency of sync signal VSYNC. Thereby, value VARIANCE isindicative of the stability of signal VSYNC. A larger value of valueVARIANCE is indicative of a less stable frequency.

Word SyncCounter is compared to a value equal to 2N/3, as shown in astep 304. If both the value of word SyncCounter is smaller than 2N/3 andcomputed value VARIANCE is greater than a threshold value equal to V1,for example, 500, then signal VSYNC is deemed to be absent or too weak,as shown in state 307 via a path 304 a. Similarly, word SyncCounter iscompared to a value equal to 5N/6, as shown in a step 305. If both thevalue of word SyncCounter is smaller than 5N/6 and value VARIANCE isgreater than a threshold value equal to V2, for example, 1500, thensignal VSYNC is also deemed to be absent or too weak, as shown in state307 via a path 305 a. Thus, in step 304, in which a larger frequencydeviation occurs from the expected frequency than in step 305, a smallervalue of variance VARIANCE than in step 305 will result in adetermination that signal VSYNC is invalid. When signal VSYNC is deemedto be absent or too weak, the invalidity determination is used, forexample, for blanking a displayed picture on display screen, not shown,in display 64 of FIG. 1 and for displaying, instead, a banner for theuser that indicates absent or too weak signal VSYNC.

As shown in a step 306, the last step in the routine, the value VARIANCEis tested by itself. If the value VARIANCE is equal to zero, that isindicative of a highly stable frequency of vertical synchronizationsignal VSYNC, the signal VSYNC is deemed to be valid, as shown in astate 309. Otherwise, as shown in a state 308, the most recently madedetermination, either that signal VSYNC is deemed to be valid orinvalid, is maintained unchanged.

Thus, in carrying out another inventive feature, microprocessor unit 73changes to a validity determination in step 306 the invaliditydetermination obtained formerly in one of steps 301, 302, 304 or 305,when value VARIANCE produced presently is lower than any of thresholdvalues V1 and V2 in a manner to provide hysteresis. For example, a lessthan a significant deterioration of the frequency stability of signalVSYNC will not change a prior determination that signal VSYNC is valid.On the other hand, signal VSYNC having less than a highly stablefrequency will not change a prior determination that signal VSYNC isinvalid.

Advantageously, the determination that signal VSYNC is deemed to bevalid does not necessitate its frequency to be exactly equal to theexpected frequency. Therefore, the determination will be valid even withrespect to signal VSYNC produced in a video recorder operating in, forexample, a fast forward mode having a frequency that deviates somewhatfrom the expected frequency.

1. A video display apparatus, comprising: a source of a periodicsynchronization signal for synchronizing an operation of a displaydevice responsive to an accompanying video signal that provides pictureinformation; a utilization circuit operating in a normal operation mode,when said synchronization signal is valid, and in a second operationmode, when said synchronization signal is invalid; and a processorresponsive to said synchronization signal and coupled to saidutilization circuit for producing a value indicative of a statisticalvariance of a frequency of said synchronization signal to change themode of operation of said utilization circuit from said normal operationmode to said second operation mode, when the statistical varianceexceeds a first threshold value.
 2. The video display apparatusaccording to claim 1 wherein said processor counts a number ofoccurrences of said synchronization signal, during a first interval, andwherein, when the counted number of occurrences is outside a normaloperation range of values, the mode of operation of said utilizationcircuit changes from said normal operation mode to said second operationmode, regardless of said statistical variance indicative value.
 3. Thevideo display apparatus according to claim 2 wherein said normaloperation range of values of the counted number of occurrences extendsbetween a lower limit and an upper limit.
 4. The video display apparatusaccording to claim 1 wherein said processor produces a plurality ofvalues corresponding to successive occurrences of said synchronizationsignal, a given value of said plurality of values being indicative of alength of an interval that has elapsed from a preceding occurrence ofsaid synchronization signal, and wherein said processor produces saidstatistical variance indicative value in accordance with a differencebetween said given value of said plurality of values and a mean value ofsaid first plurality of values.
 5. The video display apparatus accordingto claim 4 wherein said processor produces a first plurality of valuescorresponding to successive occurrences of said synchronization signal,a given value of said first plurality of values being indicative of alength of an interval that has elapsed from a preceding occurrence ofsaid synchronization signal, and wherein said processor produces saidstatistical variance indicative value from a second plurality of values,a given value of said second plurality of values being produced inaccordance with a square of a difference between a corresponding valueof said first plurality of values and a mean value of said firstplurality of values.
 6. The video display apparatus according to claim 1wherein said processor counts a number of occurrences of saidsynchronization signal, during a first interval, and wherein said firstthreshold value is selected dynamically, in accordance with said numberof occurrences.
 7. The video display apparatus according to claim 6wherein, when a deviation of said number of occurrences from an expectedvalue is larger, said selected first threshold value is smaller, andwhen said deviation is smaller, said selected first threshold value islarger.
 8. The video display apparatus according to claim 1 wherein,when said utilization circuit operates in said second mode of operationand the statistical variance is smaller than a second threshold value,operation in said normal operation mode begins and when the statisticalvariance is smaller than said first threshold value and larger than saidsecond threshold value, the operation in said normal operation modecontinues.